1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus having through-silicon vias (TSVs) and a test method thereof.
2. Related Art
With the development of semiconductor memory technology, high integration and high performance have been required for packaging technology for a semiconductor integrated circuit apparatus. Thus, in order to replace a two-dimensional (2D) structure in which semiconductor chips having an integrated circuit implemented therein are two-dimensionally arranged over a printed circuit board (PCB) through a wire or bump, a variety of three-dimensional (3D) structures have been developed in which a plurality of semiconductor chips are vertically stacked.
The 3D structure may be implemented through stack packaging technology. The stack package technology may be roughly divided into technology for packaging stacked semiconductor chips at a time and technology for stacking individually-packaged semiconductor chips.
The semiconductor chips stacked in a vertical direction to a surface of the semiconductor chip are mounted on a substrate for a semiconductor package, while electrically coupled to each other through metallic wires or TSVs.
When metallic wires are used in a stack package, performance may be reduced because electrical signals are exchanged through the metallic wires has long length. Since a large number of wires are used, electrical characteristics for example, a short between neighboring wires, may be degraded. Furthermore, since the semiconductor substrate may require an additional area to prevent the short between the neighboring wires, the entire size of the package may be increased. Since a gap for wire bonding between the semiconductor chips is required, the height of the package may be increased.
On the other hand, a stack package using TSVs has a structure which couples semiconductor chips in a vertical direction so as to couple transistors or interconnections formed over a chip to the bottom of the chip. The stack package may reduce a distance between the upper and lower chips to thereby reduce a signal loss, than the stack package having the wire bonding structure. Thus, high-speed and low-power communication may be realized between the chips. In particular, when the TSV is electrically applied as a power line, an off-chip driver may be designed to have low power consumption. Thus, the duration of use for mobile electronic products may be increased to secure high marketability.
Referring to FIG. 1, the semiconductor memory device includes a plurality of chips 10_1, 10_2, and 10_3 which are physically and electrically stacked using TSVs 20. Each of the chips has a cell area and a peripheral circuit area for realizing the function of the semiconductor memory device.
Among the plurality of chips, the chip 10_1 positioned at the lowermost part is a master chip to buffer an external signal applied from an external controller, and the chips 10_2 to 10_n positioned over the master chip 10-1 are slave chips which are physically or electrically connected to the master chip 10-1 using the TSVs 20.
Referring to FIGS. 2 and 3, the TSV 20 is formed through a silicon substrate 30, that is, each chip 10-1, 10-2, or 10-3. The silicon substrate 30 is a P-type silicon substrate having a low doping concentration or N-type silicon substrate having a low doping concentration. The TSV 20 is made of a conductive material including a metal such as copper (Cu). Furthermore, an insulating material 40 made of thin silicon oxide (SiO2) is formed between the TSV 20 and the silicon substrate 30.
Thus, the TSV 20 and the peripheral structure thereof may form a MOS capacitor structure, which includes the TSV 20 made of a conductive material, the insulating material 40, and the silicon substrate 30.
As such, the TSV 20 is provided to couple the plurality of chips 10_1, 10_2, and 10_n and is additionally formed in a completed semiconductor memory device. Thus, in order for the semiconductor memory device to perform an accurate operation and in order to develop the packaging technology for 3D structures, a test should be performed on the TSV.
However, a TSV test is performed after packaging is completed. That is, a TSV has been tested in a state where a plurality of chips are stacked and completely packaged. Then, when a fail is discovered in the tested TSV, the failed TSV is replaced to a redundancy TSV.
Therefore, a necessary number of redundancy TSVs should be prepared according to a TSV fail ratio. When fails of the TSV are larger than the prepared redundancy TSVs, the entire stack package should be discarded. Furthermore, when a fail is not discovered in the TSV, the prepared redundancy TSVs become useless. Thus, the fabrication cost inevitably increases due to the unnecessary redundancy TSVs.